A conventional emitter follower circuit includes first and second NPN transistors. The first NPN transistor for emitter follower is connected at a base to an input terminal to which an input potential V.sub.IN is applied, at a collector to a first power supply V.sub.CC, and at an emitter to an output terminal at which an output potential V.sub.OUT is obtained. The second NPN transistor is connected at a collector to the output terminal and at an emitter to a second power supply V.sub.EE, and is clamped at a base to a constant potential V.sub.S to make a constant current I.sub.S flow through the second NPN transistor.
In operation, when a high level potential is applied to the base of the first NPN transistor through the input terminal, a current larger than the constant current I.sub.S flows through the first NPN transistor to increase the output potential V.sub.OUT. The output potential V.sub.OUT is clamped to a level, that is, a level lower than the input potential V.sub.IN by approximately a forward voltage V.sub.F between the base and the emitter of the first NPN transistor, so that an emitter current of the first NPN transistor and the constant current I.sub.S are balanced. When a low level potential is applied to the base of the first NPN transistor through the input terminal, the second NPN transistor decreases the output potential V.sub.OUT. The output potential V.sub.OUT is clamped to a level, that is, a level lower than the input potential V.sub.IN by approximately a forward voltage V.sub.F between the base and the emitter of the first NPN transistor, so that an emitter current of the first NPN transistor and the constant current I.sub.S are balanced.
A conventional wired OR logic circuit includes first to third NPN transistors. The first NPN transistor is connected at a base to a first input terminal to which a first input potential V.sub.IN1 is applied, at a collector to a first power supply V.sub.CC, and at an emitter to an output terminal. The second NPN transistor is connected at a base to a second input terminal to which a second input potential V.sub.IN2 is applied, at collector to the first power supply V.sub.CC, and at an emitter to the output terminal. The third NPN transistor is connected at a collector to the output terminal and at an emitter to a second power supply V.sub.EE, and is clamped at a base to a constant voltage V.sub.S to make a constant current I.sub.S flow through the third NPN transistor.
In operation, when both or either of the first and second input potentials V.sub.IN1 and V.sub.IN2 are high level, both or either of the first and second NPN transistors which are applied at the base with a high level increases the output potential V.sub.OUT to be a level lower than the high input level by the forward voltage V.sub.F between the base and the emitter thereof. When both the first and second input potentials V.sub.IN1 and V.sub.IN2 are low level, the output potential V.sub.OUT is decreased to be a level lower than the low input level by the forward voltage V.sub.F.
According to the conventional emitter follower and wired OR logic circuits, however, there is a disadvantage in that the stand-by current is large, because the constant current flows continually through the second NPN transistor independently of the level of the input potential. The large stand-by current causes increase of the power consumption of the circuit. Additionally, such a large stand-by current decreases the merit in a Bi-CMOS circuit which has an advantage of low power consumption.
Further, a speed of increasing the output potential results in slow level, because the pull-down NPN transistor make the constant current flow even in a transit state where the pull-up NPN transistor is increasing the level of the output potential. Increase of the pull-down speed of the output potential causes increase of the constant current.